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Apache Design Solutions, the technology
leader in power and noise solutions for
chip-package-systems (CPS) convergence,
announced that Sigma Designs, a leader in
digital media processing system-on-chip
(SOC) solutions for consumer electronics,
adopted Apache's register transfer level (RTL)
to sign-off power and noise integrity products.
PowerArtist-XP™ provides a complete RTL
power optimization platform with fully
integrated advanced analysis and automatic
reduction. RedHawk™ enables full-chip
dynamic power analysis from early-stage design
to sign-off.
In September 2009, Apache acquired
Sequence Design, expanding the company's
product offerings from the earliest stages of
RTL design all the way to the physical sign-off
level. Sigma Designs chose Apache to analyze
power as early in the design flow as possible
for maximum impact on cost control and chip
power.
For additional information, contact:
(T) 408-457-2000
(E) sales@apache-da.com
(W) www.apache-da.com
ICsense is an IC design house with core
competence in analog, mixed-signal and high-voltage
IC design. The company offers best-in-class
IC design services from consultancy and
building block design up to complete turnkey
application-specific IC (ASIC)/SOC solutions.
The mission of ICsense is to be the number
one long-term partner for innovative high-performance
mixed-signal and high-voltage
customer-specific IC developments. ICsense
tackles these developments with a highly skilled
and passionate engineering team, a structured
IC design methodology, ISO 9001:2000
certified quality procedures, and close
cooperation with its customers and partners.
The company offers customer-specific ASIC
turnkey solutions, from idea to final product,
including feasibility study, system definition
and modeling, design, layout, prototyping,
prototype testing, production test and assembly
coordination. ICsense has key IC design
experience in power management, high-voltage
IC design, drivers, microelectromechanical
systems (MEMS), sensor and actuator
interfacing ICs, analog-to-digital converters
(ADCs), digital-to-analog converters (DACs),
timing circuits and ultra low-power design.
For additional information, contact:
Wim Claes
(T) 32-16-58970
(E) sales@icsense.com
(W) www.icsense.com
Magma Design Automation, a provider of
chip design software, introduced SiliconSmart®
ACE, a next-generation intellectual property
(IP) characterization and modeling tool and
the latest addition to the industry-standard
SiliconSmart product line. By leveraging new
ACE technology and embedding Magma's
ultra-fast FineSim™ simulation program with
IC emphasis (SPICE) simulator, the fully
automated SiliconSmart ACE flow delivers
more accurate models and faster turnaround
time than other tools, setting a new standard
in IP characterization and modeling for
designs targeted at 28nm and smaller process
nodes. SiliconSmart ACE is an advanced
characterization system that automatically
performs static structural analysis on transistor-level
netlists of simple standard cells and
very complex custom cells or macros. It uses
the results of this analysis to set up complete
characterization constraints and then leverages
the foundry-certified, highly accurate and
ultra-fast FineSim SPICE simulator to increase
the overall throughput of timing, power, noise
and statistical static timing analysis (SSTA)
model generation.
For additional information, contact:
(T) 408-565-7500
(E) info@magma-da.com
(W) www.magma-da.com
Mentor Graphics is a world leader in
electronic design automation (EDA) products,
consulting services and award-winning
support for electronics and semiconductor
companies. Mentor offers solutions that
meet the demand for short design cycle time,
improved productivity and acceptable yield.
Its solutions include tools for electronics
system-level design and simulation, embedded
hardware and software co-development, system
and IC verification, IC physical design and
verification, yield enhancement and testing
of sub-65nm ICs. Mentors' products include
the Olympus-SOC place-and-route system;
the Calibre physical verification suite; Calibre
design-for-manufacturability (DFM) solutions
for random, systematic and parametric issues
affecting yield; and the comprehensive Tessent
suite for production test, built-in self-test,
failure diagnosis and accelerated yield learning.
For additional information, contact:
Gene Forte
(T) 503-685-1193
(E) gene_forte@mentor.com
(W) www.mentor.com
Mixel, the leader in mobile mixed-signal IP,
announced the availability of the first Mobile
Industry Processor Interface (MIPI)/Mobile
Display Digital Interface (MDDI) unified
physical layer (PHY) IP solution. The MXLPHY-MMU-RX3 combines a MIPI D-PHY
compliant with revision 1.0 of the MIPI
standard with an MDDI-PHY compliant with
revision 1.2 of the MDDI standard.
Mixel is a leading provider of mixel-signal
IP cores to the semiconductor and electronics
industries. Mixel's mixed-signal IP portfolio
includes high-performance PHYs, serializer/deserializer (SerDes), transceivers, phase-locked
loops (PLLs), delay-locked loops
(DLLs) and analog building blocks, which
are used in mobile applications such as MIPI,
MDDI, networking and storage.
For additional information, contact:
(E) marketing@mixel.com
(W) www.mixel.com
MoSys, a leading supplier of high-density
embedded memory and high data rate
parallel and serial interface IP, announced the
availability of its silicon-proven double data
rate, third generation (DDR3) and DDR3/2
combo PHYs. MoSys' fully integrated solution
complies with the latest DDR PHY Interface
(DFI) specification and provides the PHY
interface between the controller logic and
DDR3/2 DRAM devices. The DDR3/2 PHYs
can achieve data rates up to 1600Mbps in a
wirebond package and 2133Mbps in flip-chip
packaging, making them well-suited for both
high-performance and cost-sensitive designs.
For additional information, contact:
(T) 408-731-1800
(E) ip@mosys.com
(W) www.mosys.com
Novocell Semiconductor announced the
development of 2nTP™, a new multi-time
programmable (MTP) technology that
allows for the programming of its one-time
programmable (OTP) antifuse bit cell up to
eight times. 2nTP can be configured as a two,
four or eight times write, and it is based on the
NovoBlox™ bit cell, a non-volatile memory
(NVM) already proven at leading foundries.
NovoBlox is a OTP memory IP that can be
embedded in standard logic CMOS without
any additional process steps or post processing.
Novocell specializes in providing advanced
NVM IP for use in the industrial, consumer
electronic and communications industries.
For additional information, contact:
Steve Warner
(T) 724-983-0600
(E) steve@novocellsemi.com
(W) www.novocellsemi.com
Oracle provides industry-leading business
solutions for the semiconductor industry based
on best-of-breed applications; middleware;
and open, standards-based technology. Oracle's
supply chain solution helps semiconductor
companies achieve accurate consensus
forecasts, optimized inventory leveling and
postponement strategies, faster planning cycles
and superior on-time delivery. While Oracle's
acquisitions have certainly added value to their
comprehensive solution capabilities, few have
recognized the continual innovation of new
functionality which stems from their annual
research and development (R&D) efforts,
worth $3 billion annually. This fall Oracle
will release a newly developed standalone
product, Oracle Rapid Planning. The product
will answer the "what if" questions that arise
and will allow supply chain planners to react
in minutes to rapidly changing conditions
and exceptions in a semiconductor company's
complex, multi-tiered supply chain. Using
an intuitive new user interface (UI) and an
event-based, scalable, incremental planning
engine, Oracle Rapid Planning enables a real-time
planning paradigm providing capabilities
to simulate the impact of events and use
embedded analytics to gain predictive and
actionable insight. Please contact Oracle to
request a demo of the new Oracle Rapid
Planning.
For additional information, contact:
(T) 800-633-0738
(W) www.oracle.com/industries/semiconductor
Sidense provides secure, very dense and
reliable non-volatile OTP memory IP for
use in standard-logic CMOS processes
with no additional masks or process steps
required and no impact on product yield. The
Company's innovative one-transistor (1T)-Fuse™ architecture provides the industry's
smallest footprint, most reliable and lowest
power NVM IP solution. With over 40 patents
granted or pending, Sidense OTP provides
a field-programmable alternative solution
to Flash, mask read-only memory (ROM)
and eFuse in many OTP and Media Transfer
Protocol (MTP) applications.
Sidense OTP memory IP is available from
180nm down to 55nm and is scalable to 28nm
and below. It is available and has been adopted
from all top-tier semiconductor foundries
and selected integrated device manufacturers
(IDMs). Customers use Sidense's OTP
memory for analog trimming, code storage,
encryption keys such as High-bandwidth
Digital Content Protection (HDCP), radio
frequency identification (RFID) and chip
ID, medical, automotive, and configurable
processors and logic.
For additional information, contact:
Jim Lipman
(T) 925-606-1370
(E) jim@sidense.com
(W) www.sidense.com
SiliconXpress is a semiconductor company
with offices in Lubbock, Texas and Santa
Clara, California. The company offers full
turnkey 100 percent domestic content from
RTL development to packaged and tested
silicon. SiliconXpress maintains the necessary
clearances required for customers' trusted
programs. With the exception of foundry
services, all other IC services, including design,
packaging and testing, are performed in-house.
For additional information, contact:
Aftab Farooqi
(T) 806-698-0118 ext. 100
(E) aftab.farooqi@siliconxpress.com
(W) www.siliconxpress.com
Sofics is the leading on-chip electrostatic
discharge (ESD) solutions and IP provider,
well known for its TakeCharge specialty ESD
solutions in low-voltage sub-micron and
nano CMOS technology. Recently, Sofics
announced a new portfolio called PowerQubic,
which is comprised of ESD solutions with
amazing breakthrough characteristics for
high-voltage and power IC applications and
processes. These characteristics include high
ESD robustness (scalable 2kV-4kV-8kV-); very
low leakage (~nA at 25C, ~100nA at 125C);
guaranteed latch-up immune with full current
clamping above the high-voltage supply level
and across the full temperature range; smallest
silicon area footprint; lowest capacitance;
tunable trigger and holding current and voltage
(Vt1, It1, Vh, It2, Vt2); and cost-effective ESD
protection reliability for supply pins as well as
for input/output (I/O) interfaces, switches and
large driver circuits. For more information on
PowerQubic hebistors, download and read the
company's free whitepaper at www.sofics.com/files/WP-2010-Q1-1.pdf.
For additional information, contact:
Pieter Donck
(T) 32-9-21-68-341
(E) pdonck@sofics.com
(W) www.sofics.com
Virage Logic's new ARC 601 32-bit
microprocessor core offers the best-in-class
combination of small size and low power with
excellent performance. Designers can tailor
the highly configurable ARC 601 to meet
their specific application needs by excluding
features that are not required, thereby reducing
area, power consumption and cost. The ARC
601 runs at 532MHz (1.2 DMIPS/MHz),
consuming just 13μW/MHz in 65nm process
technology. At only 0.039mm2, the ARC 601
will fit two and a half times into the size of a
period (12-point font) at the end of a sentence.
The processor is available today and has already
been licensed to several of Virage Logic's lead
customers.
For additional information, contact:
Sabina Burns
(T) 510-743-8115
(E) sabina.burns@viragelogic.com
(W) www.viragelogic.com
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